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Espressif Systems /ESP32-S3 /LCD_CAM /LC_DMA_INT_ST

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Interpret as LC_DMA_INT_ST

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LCD_VSYNC_INT_ST)LCD_VSYNC_INT_ST 0 (LCD_TRANS_DONE_INT_ST)LCD_TRANS_DONE_INT_ST 0 (CAM_VSYNC_INT_ST)CAM_VSYNC_INT_ST 0 (CAM_HS_INT_ST)CAM_HS_INT_ST

Description

LCD_camera DMA masked inturrupt status register

Fields

LCD_VSYNC_INT_ST

The status bit for LCD frame end interrupt.
LCD_TRANS_DONE_INT_ST

The status bit for lcd transfer end interrupt.
CAM_VSYNC_INT_ST

The status bit for Camera frame end interrupt.
CAM_HS_INT_ST

The status bit for Camera transfer end interrupt.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data